1. Field of the Invention
The present invention relates to a processor to execute in parallel a plurality of instructions using a plurality of functional units, and an instruction allocation controller. Particularly, the present invention relates to a processor in which the VLIW (very-long-instruction-word) system that executes in parallel a plurality of instructions at the same time using a plurality of functional units is applied, and an instruction allocation controller.
2. Description of the Background Art
When a single instruction is executed by a microprocessor, the register in which the operation result is to be stored is specified, and the content of the special register called the flag register is modified, if necessary. The VLIW and superscaler type CPU architectures which have been recently developed are directed to execute instructions in parallel. When a plurality of instructions are to be executed at the same time by the superscaler, the task of allocating each instruction to an appropriate one of the functional unit must be carried out every time. In contrast, since a functional unit in which an instruction is executed is determined on creating a program for a VLIW type processor among a plurality of functional units, the hardware for such a processor can be reduced compared to the one employing superscaler architecture.
Although the microprocessor in which the VLIW is applied can execute a plurality of instructions simultaneously by including a plurality of functional units, it sometimes happens when a flag register is to updated by a plurality of instructions executed in parallel. This is referred to as xe2x80x9cconflictxe2x80x9d. Such a conflict is not preferable since execution of the program will look as if it has stopped when such a conflict occurs. In order to avoid this conflict state, the executing order of the instructions must be scheduled in advance so that a plurality of instructions that will update the content of the flag register are not executed simultaneously. This leads to a decreased number of instructions that are executed in parallel, which means degrading the throughput. There is also the problem that the program is increased m size.
An object of the present invention is to provide a processor and an instruction allocation controller that can improve the throughput.
Another object of the present invention is to provide a processor and an instruction allocation controller that can reduce the size of the program to be executed.
According to an aspect of the present invention, a processor includes a plurality of functional units. When a plurality of instructions in the program are executed in parallel using a plurality of functional units, determination is made in advance of which of the plurality of functional units is used for execution of respective instructions.
The processor includes a register in which control information that is shared by the plurality of functional units for program execution control is stored and accessed in common by the plurality of functional units, and an arbitration unit arbitrating access according to predetermined priority of control information access among the plurality of functional units when the content of the register is to be simultaneously accessed by the plurality of functional units in the parallel execution of a plurality of instructions.
When simultaneous access of the control information in the register is attempted by a plurality of functional units in program execution in the processor, the access from only one functional unit is made valid by the arbitration unit according to the predetermined priority. As a result, a conflict among the plurality of functional units as to the control information in the register can be avoided.
Since the execution order of instructions does not have to be scheduled to avoid a conflict of access of control information among the plurality of functional units, the number of instructions that can be substantially executed at the same time can be increased than the conventional case. More specifically, the substantial throughput becomes higher, and the size of the program is reduced.
In the register of the processor of the present aspect, control information provided individually for each of the plurality of functional units associated with execution control of the program are also stored.
The arbitration unit includes a first arbitration unit selectively setting a share mode in which the access of shared control information is arbitrated according to the predetermined priority among the plurality of functional units and a discrete mode in which respective individual control information is accessed by a corresponding functional unit when the plurality of functional units attempt to access simultaneously the content of the register in parallel execution of a plurality of instructions.
Therefore, when the content of the register is to be accessed simultaneously by a plurality of functional units in the parallel execution of a plurality of instructions and the share mode is set at the first arbitration unit, the shared control information in the register is accessed according to the predetermined priority among the plurality of functional units. Only the access from one functional unit is enabled. A conflict among the plurality of functional units regarding access of the shared control information is avoided. When the first arbitration unit is set to the discrete mode, each of the plurality of functional units accesses the individual corresponding discrete control information in respective registers. Therefore, a conflict among the plurality of functional units accessing simultaneously the content of the register can be avoided.
Thus, scheduling the execution order of the instructions to avoid such a conflict is no longer required. As a result, the number of instructions that can be substantially executed at the same time increases. In other words, the substantial throughput increases and the size of the program is reduced.
In the processor of the present aspect, either the share mode or the discrete mode is selectively set according to the feature of the program. Therefore, the operational ability can be improved in the mode corresponding to the feature of the program. Also, the specification of the program can be made more versatile.
In the processor of the present aspect, the plurality of instructions include an instruction of designating simultaneously a predetermined operation on a high order half-word and a predetermined operation on a low order half-word. The control information includes at least one flag to indicate the state of a relevant predetermined operation for respective predetermined operations on the high order and low order half-words.
Therefore, the flag to indicate the state of each predetermined operation when a predetermined operation is executed for each half-word by one instruction can be retained in the register. Thus, a conflict among the plurality of functional units can be avoided even when the instruction designating simultaneous predetermined operation on the high order half-word and low order half-word is executed in any of the plurality of functional units in the processor. Such an instruction can be used in a wider application. The development tool of the software can be made more versatile.
In the processor of the present aspect, determination of which of the plurality of functional units is used to execute respective plurality of instructions is made at the stage of assembling the program.
In the present aspect, the processor further includes a particular functional unit differing from the plurality of functional units. The particular functional unit applies a predetermined operation on the control information and writes the value of the result into the register as control information.
Thus, the particular functional unit applies a predetermined operation on the control information that is accessed by a plurality of functional units and writes the resulting value into the register as the control information. Therefore, the generic status of the operation in the processor can be identified by just referring to the register content with no particular postprocess. The program can be reduced in size and complexity.
According to another aspect of the present invention, a processor includes a plurality of functional units. The processor is predetermined of which of the plurality of functional units is used for execution of respective plurality of instructions when a plurality of instructions in the program are to be executed in parallel by a plurality of functional units.
The processor of the present aspect includes a register in which discrete control information regarding execution control of a program provided for each of the plurality of functional units is stored and shared by respective plurality of functional units, and an arbitration unit to have each discrete control information accessed individually by a corresponding functional unit when the plurality of functional units attempt to access simultaneously the content of the register when the parallel execution of a plurality of instructions.
When the plurality of functional units attempt to access the content of the register at the same time, a corresponding discrete control information is accessed individually by each functional unit. A conflict regarding the access of the execution control information of the program in the register by the plurality of functional units encountered in the conventional case is avoided.
It is therefore not necessary to schedule the execution order of the instructions to prevent simultaneous execution of instructions that access information regarding execution control of a program in the register. As a result, the number of instructions that can be executed substantially at the same time can be increased than in the conventional case. More specifically, the substantial throughput is improved. Also, the program size is reduced.
In the processor of the present aspect, the plurality of instructions include an instruction of designating simultaneously a predetermined operation on a high order half-word and a predetermined operation on a low order half-word. The control information includes at least one flag to indicate the status of a relevant predetermined operation for respective operations on the high order and low order half-words.
Therefore, the flag to indicate the status of each predetermined operation when a predetermined operation is executed for each half-word by one instruction can be retained in the register. The above-described a conflict among the plurality of functional units can be avoided even when an instruction that designates simultaneous predetermined operation on a high order half-word and on a low order half-word in the processor is executed by any of the plurality of functional units. Such an instruction can be used in a wider application. The development tool of the software can be made more versatile.
In the processor of the present aspect, determination of which of the plurality of functional units is used to execute respective instructions is made at the assembling stage of the program.
The processor of the present aspect further includes a particular functional unit different from the plurality of functional units. The particular functional unit applies a predetermined operation on discrete control information and writes a resultant value into the register as discrete control information.
Therefore, the generic status of the operation in the processor can be identified by just referring to the content of the register. The program is reduced in size and complexity.
According to a further aspect of the present invention, an instruction allocation control method determines in advance which of a plurality of functional units is used to execute respective instructions for a processor including a plurality of functional units and that executes a program by processing a packet that includes a plurality of fields corresponding to the plurality of functional units and in which a plurality of instructions of the program is stored.
The processor further includes a register that is accessed in common by a plurality of functional units, and in which control information shared by a plurality of functional units regarding execution control of a program is stored. The instruction allocation control method includes a read step of sequentially reading an instruction from a program, and a storage step of allocating and storing the instruction read by the read step to any field in the packet.
The storage step includes a simultaneous access determination step, an allocation determination step, and an allocation step. The simultaneous access determination step determines whether or not the content of the register is accessed simultaneously by the plurality of functional units when a subsequent instruction read in by the read step and a prior instruction already stored in the packet are executed in parallel. The allocation determination step responds to determination of simultaneous access by the simultaneous access determination step to determine whether the prior instruction and the subsequent instruction can be allocated to a field in the same packet according to a predetermined priority. In the allocation step, the prior instruction and the subsequent instruction are respectively allocated to a plurality of fields in the same packet so as to be executed in parallel according to determination of admissible allocation by the allocation determination step, and the prior instruction and the subsequent instruction are respectively allocated to a plurality of fields in the same packet so as to be executed serially according to determination of inadmissible allocation. The predetermined priority corresponds to the priority among the plurality of functional units as to the access of the control information.
According to the instruction allocation control method of the present aspect, a conflict among the plurality of functional units regarding access of control information in the processor when executing a program can be avoided.
Since instructions that access simultaneously control information in instruction execution can be stored in the same packet and applied to the processor, the number of instructions that can be executed at the same time in the processor is increased. Therefore, the substantial throughput is improved. Also, the size of the program is reduced.
The instruction allocation control method of the present aspect is further characterized as follows. The register is set to the operation mode of either a share mode or a discrete mode. In the share mode, the control information shared by the plurality of functional units is stored in the register. In the discrete mode, the control information provided individually for each of the plurality of functional units are stored in the register. The instruction allocation control method further includes a mode set step, a predetermined process step and an execution step. When the instruction read in by the read step is a mode modify instruction that specifies modification of the operation mode of the register, the operation mode of the register is set according to that information in the mode set step. When the discrete mode is set by the mode set step, a predetermined process is executed for the instruction read in by the read step in the predetermined process step. When the share mode is set by the mode set step, the aforementioned storage step is carried out for the information read in by the read step in the execution step.
Since the operation mode of the register can be arbitrarily set variable in the program to be executed, the operation mode of the register can be modified at the user side as desired according to the feature of the program. The operation performance can be further improved.
The instruction allocation control method of the present aspect is applied in the assemble stage prior to execution of the program.
According to still another aspect of the present invention, an instruction allocation controller determines in advance which of the plurality of operation units is used to execute respective plurality of instructions for a processor. The processor includes a plurality of functional units and executes a program by processing with the plurality of functional units a packet that includes a plurality of fields in which a plurality of instructions of the program are stored and corresponding to the plurality of functional units.
The processor further includes a register in which control information shared by the plurality of functional units regarding execution control of the program is stored and accessed by the plurality of functional units.
The instruction allocation controller includes a read unit to sequentially read in an instruction from the program, and a storage unit to allocate and store the instruction read in by the read unit to any of the fields in the packet for storage. The storage unit includes a simultaneous access determination unit, an allocation determination unit and an allocation unit. The simultaneous access determination unit determines whether the content of the register is accessed simultaneously by the plurality of functional units when a subsequent instruction read in by the read unit and a prior instruction prestored in the packet are executed in parallel. The allocation determination unit responds to determination of simultaneous access by the simultaneous access determination unit to determine whether the prior instruction and the subsequent instruction can be allocated to a field in the same packet according to a predetermined priority. The allocation unit responds to determination of admissible allocation by the allocation determination unit to allocate the prior instruction and the subsequent instruction to a plurality of fields in the same packet so as to be executed in parallel, and responds to determination of inadmissible allocation to allocate the prior instruction and the subsequent instruction to a plurality of fields in the same packet so as to be executed serially. The predetermined priority corresponds to the priority among the plurality of functional units as to access of control information.
According to the present aspect, contention among the plurality of functional units regarding access of control information in the processor during program execution can be avoided.
Since instructions that access control information simultaneously in instruction execution are stored in the same packet and applied to the processor, the number of instructions that can be executed simultaneously in the processor is increased. The substantial throughput is improved. Also, the size of the program is reduced.
The instruction allocation control of the present aspect is further characterized as follows.
The register is set to an operation mode of either a share mode or a discrete mode. In the share mode, control information shared by the plurality of functional units is stored into the register. In the discrete mode, control information provided individually for each of the plurality of functional units are stored into the register. The instruction allocation controller further includes a mode set unit, a predetermined process unit and an execution unit. When the instruction read in by the read unit is a mode modify instruction designating modification of the operation mode, the operation mode of the register is set according to that instruction in the mode set unit. When the discrete mode is set by the mode set unit, a predetermined process is executed for the instruction read in by the read unit in the predetermined process unit. When the share mode is set by the mode set unit, the above-described storage unit is executed for the read instruction in the execution unit.
Since the operation mode of the register can arbitrarily be set variable in the program to be executed, the operation mode of the register can be modified as desired by the user according to the feature of the program. The operation ability can further be improved.
In the present aspect, the allocation controller is applied to the assembler for setting the program in an execution format.
A still further aspect of the present invention relates to a computer-readable recording medium in which an instruction allocation control program to have an instruction allocation control method executed by the computer is recorded. The instruction allocation control method predetermines which of a plurality of functional units is used to execute respective plurality of instructions for a processor. The processor includes a plurality of functional units and executes a predetermined program by processing with the plurality of functional units a packet including a plurality of fields corresponding to the plurality of functional units and in which a plurality of instructions of the predetermined program are stored.
The information process further includes a register in which is stored control information shared by the plurality of functional units regarding execution control of the predetermined program. The control information is accessed in common by the plurality of functional units. The instruction allocation control method includes a read step of sequentially reading in an instruction from the predetermined program, and a storage step of allocating and storing the instruction read in by the read step into any of the fields of the packet.
The storage step includes a simultaneous access determination step, an allocation determination step and an allocation step. The simultaneous access determination step determines whether the content of the register is accessed simultaneously when a subsequent instruction read in by read step and a prior instruction already stored in the packet are executed in parallel. The allocation determination step responds to determination of simultaneous access by the simultaneous access determination step to determine whether the prior instruction and the subsequent instruction can be allocated to a plurality of fields in the same packet according to a predetermined priority. The allocation step responds to admissible allocation determination by the allocation determination step to respectively allocate the prior instruction and the subsequent instruction to the plurality of fields in the same packet so as to be executed in parallel, and responds to determination of inadmissible allocation to respectively allocate the prior instruction and the subsequent instruction to the plurality of fields of the same packet so as to be executed serially. The predetermined priority corresponds to the priority determined among the plurality of functional units regarding access of control information.
Since instructions that access control information during execution can be allocated simultaneously to the plurality of functional units, scheduling is no longer required to prevent simultaneous allocation of a plurality of instructions that access the control information to a plurality of functional units as in the conventional case.
Since instructions that simultaneously access control information during instruction execution can be stored together in the same packet and applied to the processor, the number of instructions that can be executed at the same time in the processor is increased. The substantial throughput is improved. Also, the program is reduced in size.
The recording medium of the present aspect is further characterized as follows.
The register is set to the operation mode of either a share mode or a discrete mode. When in a share mode, control information that is shared by the plurality of functional units is stored. When in a discrete mode, control information that is provided individually for respective plurality of operation units is stored. The instruction allocation control method further includes a mode modification step, a predetermine process step and an execution step. When the instruction read in by the read step is a mode modify instruction designating modification of the operation mode of the register in the mode modification step, the operation mode of the register is set according to that instruction. When the discrete mode is set by the mode set step, a predetermined process is executed for the read instruction in the predetermined process step. When the share mode is set by the mode set step, the storage step is executed for the read in instruction in the execution step.
Since the operation mode of the register can be arbitrarily set variable in the executed predetermined program, the operation mode of the register can be modified as desired by the user according to the feature of the predetermined program. Therefore, the operation ability can be further improved.
The recording medium of the present aspect is further characterized in that the instruction allocation control method is applied in the assemble stage prior to execution of the predetermined program.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.